Recent Advances in Electrical & Electronic Engineering - Volume 18, Issue 7, 2025

Higher power consumption raises chip temperature because it draws more current from the power source, which directly affects how long the batteries survive in portable devices. High temperature affects the dependability and functionality of a circuit, requiring more complex packaging and cooling strategies. One of the most significant challenges in VLSI design is power consumption. The power consumption of the circuit rises with both transistor density and chip complexity. In addition, one of the essential building blocks of hardware in the majority of VLSI applications and digital signal processing systems is the multiplier.

This study aimed to design and compare array multiplier, Vedic multiplier, and Wallace tree multiplier using variable bit lengths.

In this paper, authors designed array multiplier, Vedic multiplier, and Wallace tree multiplier using variable bit lengths. For comparison, the VIVADO tool was used to simulate and synthesize multiplier outputs.

Wallace tree multipliers resulted in 31.153mW, 13.220mW, 4.099mW, and 0.988 mW of power dissipation for 16-bit, 8-bit, 4-bit, and 2-bit, respectively. The best multiplier was designed using different logic like AOI, OAI, NAND-NAND, and NOR-NOR and was compared based on power dissipation. It was observed that 2.256mW power dissipation was observed for NOR-NOR logic, which was minimal among other logics.

The 4-bit Wallace multiplier using NOR-NOR logic was used for FPGA implementation, which can be used in digital signal processing applications.

With the advancement in technology nodes and scaling trends, the majority of the device performance depends upon the interconnections made between two or more devices. With these scaling trends, frequency plays a vital role. As the technology decreases, frequency tends to rise to giga-hertz. This increase in frequency gives rise to inductance parameters in the interconnect circuits. For long wires, the inductive impedance can become comparable to the resistive component due to which performance degradation can be observed along with overshoot and crosstalk issues that can no longer be ignored.

This article aims to examine the delay model and reconstruct an interconnect circuit that serves as a transmission line, ranging in length from 1 mm to 10 mm.

By keeping the frequency high, low voltage and rise/ fall time, performance parameters such as delay, power consumption, and overshoot are observed.

The interconnect structure is compared with another state-of-the-art technique.

Diabetes has been rising in recent years and prior research has demonstrated Machine Learning Techniques (MLTs) to be useful tools for predicting diabetes. This research has examined the accuracy of six different MLTs for predicting diabetes using lifestyle data gathered from UCI (University of California). To improve medical outcomes and prevent its onset, the prediction of diabetes is necessary. This research has proposed a new framework based on the early detection of diabetes using lifestyle factors. Various MLTs, such as Logistic Regression (LR), Decision Tree Classification (DTC), Random Forest Classification (RFC), Support Vector Classification (SVC), and K-Nearest Classification (KNC) have been used for tenfold cross-validation and the results obtained from different techniques have been verified. Among all classification techniques, LR has achieved the highest accuracy of 93%, the precision of 92%, the recall score of 94%, the F1 score of 93%, and the weighted average of 90%, respectively. The proposed framework is utilized by the healthcare sector to predict diabetes early. It can also be used with datasets from various sectors that share diabetes-related data.

In this paper, we have used the proposed framework to predict diabetes mellitus in the healthcare system, diagnose various ailments, and assess if MLA performs well. The proposed system has been developed based on the MLT for the classification of DM. An intelligent framework for Diabetes Mellitus (DM) that has been developed using MLT illustrates the full workflow from data input to output. The five algorithms, Logistic Regression (LR), Decision Tree Classification (DTC), Random Forest Classification (RFC), Support Vector Classification (SVC), and K-Nearest Classification (KNC), have been compared in terms of accuracy, precision, recall, and F1 score.

Results from the experimental setting using MLTs for DM prediction based on lifestyle predictors have been obtained. Descriptive statistics of lifestyle characteristics have been displayed along with their corresponding metrics, such as mean, standard deviation, minimum, maximum, etc. For instance, the age parameters’ mean, standard, and minimum at 25%, 50%, 75%, and maximum values were as follows: 520.0, 48.02, 12.151, 16.0, 39.0, 47.5, 57.0, and 90.0 respectively. Feature engineering is crucial to the process of constructing MLT. Insignificant or incorrect characteristics may have a negative impact on the way a model runs. The training time is drastically reduced and accuracy is increased with careful feature selection. In machine learning frameworks, some feature selection strategies include embedding, filter, wrapper, embedded, and hybrid techniques. An alarming number of people around the world suffer from the chronic and dangerous disease of diabetes. Using MLT, early DM prediction-based biological variables have been obtained in this research work. Data on patients’ lifestyles have been thoroughly examined in order to create a framework. The Canonical-correlation Analysis (CCA) has been used to select the ideal combination of lifestyle features. Finally, 10-fold cross-validations have been used to apply five alternative machine learning techniques for the prediction of disease.

To our knowledge, it is the first time a framework has been proposed that has yielded prediction results so much better than those from earlier research. The results obtained in this suggested work have been found accurate and reliable by metrics evaluation.

Parallel prefix adders are widely used in high-speed arithmetic circuits due to their ability to perform additions in logarithmic time. However, the high area and delay of exact parallel prefix adders prompted the development of approximate parallel prefix adders. These adders are a promising solution for high-speed arithmetic circuits because they sacrifice accuracy for reduced area and delay.

This paper presents a performance analysis of five approximate parallel prefix adders realized with field programmable gate array technology. The five approximate parallel prefix adders are the Kogge-Stone adder, the Sklansky adder, the Brent-Kung adder, the Han-Carlson adder, and the Ladner-Fisher. Each adder is implemented in a Xilinx Artix-7 FPGA. The area and delay of five approximate parallel prefix adders are evaluated. The Kogge-Stone approximate parallel prefix adder, out of five approximate parallel prefix adders, consumes the least delay, irrespective of the number of bits.

The Sklansky approximate parallel prefix adder out of five approximate parallel prefix adders consumes the least area irrespective of the number of bits in addition. Overall, our research sheds light on the trade-offs between area, power delay, and power delay products of five approximate parallel prefix adders implemented with FPGA technology.

This analysis can help choose the best approximate parallel prefix adder for specific high-speed arithmetic applications. In the case of 16- and 32-bit five approximate parallel prefix adders, Ladner-fisher shows the best power delay product, whereas 64- and 128-bit five approximate parallel prefix adders, Sklansky adder shows the best power delay product.

With the continuous development of permanent magnet synchronous motors (PMSM) and the increasing demand for the application of flywheel battery, the requirements for PMSMs are also increasing.

A multi-objective genetic algorithm is used to solve the optimal design solution.

Multi-objective genetic algorithm is fast and accurate in calculation results, and it is easy to obtain the optimal solution. The results show that the cogging torque is reduced by 23.6%, the torque ripple is reduced by 25%, and the average torque is increased by 1.2%.

A multi-objective optimization design was conducted on a surface-mounted PMSM. Firstly, the sensitivity of different optimization variables was calculated. The high-sensitivity parameters were selected as the final optimization variables. The response surface between the optimization variables and the optimization objectives was calculated. The genetic algorithm was used to solve the optimal design solution. The effectiveness of the optimization results was verified by the combination of finite element simulation and experimental tests.