Skip to content
2000
Volume 18, Issue 7
  • ISSN: 2352-0965
  • E-ISSN: 2352-0973

Abstract

Introduction

Parallel prefix adders are widely used in high-speed arithmetic circuits due to their ability to perform additions in logarithmic time. However, the high area and delay of exact parallel prefix adders prompted the development of approximate parallel prefix adders. These adders are a promising solution for high-speed arithmetic circuits because they sacrifice accuracy for reduced area and delay.

Methods

This paper presents a performance analysis of five approximate parallel prefix adders realized with field programmable gate array technology. The five approximate parallel prefix adders are the Kogge-Stone adder, the Sklansky adder, the Brent-Kung adder, the Han-Carlson adder, and the Ladner-Fisher. Each adder is implemented in a Xilinx Artix-7 FPGA. The area and delay of five approximate parallel prefix adders are evaluated. The Kogge-Stone approximate parallel prefix adder, out of five approximate parallel prefix adders, consumes the least delay, irrespective of the number of bits.

Results

The Sklansky approximate parallel prefix adder out of five approximate parallel prefix adders consumes the least area irrespective of the number of bits in addition. Overall, our research sheds light on the trade-offs between area, power delay, and power delay products of five approximate parallel prefix adders implemented with FPGA technology.

Conclusion

This analysis can help choose the best approximate parallel prefix adder for specific high-speed arithmetic applications. In the case of 16- and 32-bit five approximate parallel prefix adders, Ladner-fisher shows the best power delay product, whereas 64- and 128-bit five approximate parallel prefix adders, Sklansky adder shows the best power delay product.

© 2025 Bentham Science Publishers
Loading

Article metrics loading...

/content/journals/raeeng/10.2174/0123520965311872240509092528
2024-05-14
2025-09-03

  • From This Site

    /content/journals/raeeng/10.2174/0123520965311872240509092528
    dcterms_title,dcterms_subject,pub_keyword
    -contentType:Contributor -contentType:Concept -contentType:Institution
    10
    5
Loading full text...

Full text loading...

References

  1. TsuiC.Y. VLSI parallel adders: Architectures, algorithms, and applications.IEEE Trans. Comput.1984331212171227
     [Google Scholar]
  2. SahaT.K. ChowdhuryA.N. AkhandM.A.H. Low-power parallel-prefix adder designs for approximate computing.J. Low Power Electr. and Appl.2020101
     [Google Scholar]
  3. MohapatraD. SharmaR.K. MohapatraS. A low-power high-speed approximate parallel prefix adder for error-tolerant applications.J. Circuits Syst. Comput.2018277
     [Google Scholar]
  4. SinghP. KumarA. KumarA. Low power high-speed approximate parallel prefix adder for multimedia applications.J. Comput. Electron.202019411391154
     [Google Scholar]
  5. ShamsiM. MiremadiS. Mirza-AghatabarM.J. NavabiZ. Energy-efficient approximate parallel-prefix adders for multimedia applications. IEEE Transactions on Very LargeScale Integration (VLSI).Systems201523611141118
     [Google Scholar]
  6. HuangH. LiX. YangY. Low-power approximate adders with selective computation. IEEE Transactions on Very Large Scale Integration (VLSI).Systems202028614711484
     [Google Scholar]
  7. MittalS. GuptaM. GargS. Approximate adders: A comprehensive survey.ACM Trans. Embed. Comput. Syst.2020195s113
     [Google Scholar]
  8. NayakA. MahapatraA. MohantyS.K. Design and analysis of a low-power approximate parallel prefix adder using hybrid approximation techniques.IEEE Trans. Emerg. Top. Comput.202192498509
     [Google Scholar]
  9. WangY. LiuC. WangL. A survey of approximate adders for energy-efficient computing.IEEE Access202195966559677
     [Google Scholar]
  10. HuangJ. FanX. JiangY. WuQ. An area-efficient and low-power approximate parallel-prefix adder for multimedia signal processing.IEEE Trans. Ind. Electron.2015621279557964
     [Google Scholar]
  11. AliK. AzamM. HussainF. Performance evaluation of approximate parallel prefix adders for FPGA-based arithmetic circuits.Int. J. Electron. Commun.2021126153163
     [Google Scholar]
  12. AlmalagA.A. KhairatM.M. BayoumiM.A. Energy-efficient high-performance parallel prefix adder design for multimedia applications.IEEE Trans. Circuits Syst. II Express Briefs20125911804808
     [Google Scholar]
  13. VinhL.D. ChoS.R. KimH.J. Performance comparison of approximate parallel prefix adders for low-power arithmetic circuits.Int. J. Circuit Theory Appl.2021494588603
     [Google Scholar]
  14. ZhangM. LiC. ZhangY. ChenY. An energy-efficient approximate parallel prefix adder for multimedia signal processing.IEEE Trans. Multimed.201921411241134
     [Google Scholar]
  15. KumarP. KumarP. SinghK. Performance analysis of approximate parallel prefix adders for FPGA-based arithmetic circuits.Int. J. Electron.20201076907929
     [Google Scholar]
  16. SahaS.K. MaityS.P. A novel hybrid approximate parallel prefix adder for efficient arithmetic circuits.Microelectronics J.201762149161
     [Google Scholar]
  17. ZhengH. LiY. RoyK. Low-power approximate adders with efficient error compensation. IEEE Transactions on Very Large Scale Integration (VLSI).Systems2021292345355
     [Google Scholar]
  18. HanS.W. Mangione-SmithW.H. Area and delay trade-offs in the design of approximate parallel-prefix adders.IEEE Trans. Comput.2005546685697
     [Google Scholar]
  19. LiY. LiX. LiZ. LiX. Design and analysis of a low-power approximate parallel prefix adder based on the Han-Carlson algorithm.J. Electronic testing: theory applications2019353305318
     [Google Scholar]
  20. KumarR. RanganathanN. RoyK. A probabilistic approach to approximate arithmetic circuits.Proceedings of the Design Automation Conference (DAC), June 2011, pp. 21-26.
     [Google Scholar]
  21. YangH. LiuQ. XieY. Approximate parallel prefix adders.Proceedings of the International Conference on Computer-Aided Design (ICCAD), Nov. 2014, pp. 1-7.
     [Google Scholar]
  22. HanJ. KimH. Approximate parallel prefix adder based on selective carry approximation.Electron. Lett.2019551910121014
     [Google Scholar]
  23. PedramM. Approximate computation and its application to error-tolerant computing.Proceedings of the International Symposium on Low Power Electronics and Design (ISLPED), Aug. 2001, pp. 5-10.
     [Google Scholar]
  24. BanerjeeA. Ray ChowdhuryA. RoyK. Approximate adders for energy-efficient computation.IEEE Trans. Comput. Aided Des. Integrated Circ. Syst.2014331117461759
     [Google Scholar]
  25. SaxenaA. GurumurthyK.S. A survey of approximate adders and multipliers.J. Electronic Testing: Theory and Applications2019355467485
     [Google Scholar]
  26. YangH. LiuQ. XieY. Approximate parallel prefix adders for low-power digital signal processing. IEEE Transactions on Very Large Scale Integration (VLSI).Systems2017251131233136
     [Google Scholar]
  27. GuptaA. RaychowdhuryA. RoyK. Approximate counters for energy-efficient signal processing.Proceedings of the Design, Automation & Test in Europe Conference & Exhibition (DATE), , Mar. 2013, pp. 34-39.
     [Google Scholar]
  28. VenkataramaniS. RaghunathanA. JhaN.K. Approximate algorithms for energy-efficient design of error-tolerant applications. IEEE Transactions on Very Large Scale Integration (VLSI).Systems2005133353365
     [Google Scholar]
  29. SahaT.K. ChowdhuryA.N. AkhandM.A.H. Design and implementation of high-speed approximate parallel prefix adders on FPGA.Microprocess. Microsyst.201969102966
     [Google Scholar]
  30. VenkataramaniR. RaghunathanA. JhaN.K. Performance-driven design of low-power approximate adders.Proceedings of the Design Automation Conference (DAC) , June 2000 pp. 836-841.
     [Google Scholar]
  31. EsmaeilzadehH. BlemE. St. AmantR. SankaralingamK. BurgerD. Dark Silicon and the End of Multicore Scaling.Proceedings of the International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS), San Jose, California, USA, 04 June 2011, pp. 365-376.10.1145/2000064.2000108
     [Google Scholar]
  32. HashemiM. ArdalanA. KarriR. Approximate computing: An emerging paradigm for energy-efficient design.IEEE Des. Test2016331822
     [Google Scholar]
  33. ShafiqueM. AnwarM.U. HenkelJ. A survey of techniques for approximate computing.ACM Comput. Surv.201648462
     [Google Scholar]
  34. SarvariH. SedighiM. KhonsariA. NaviK. A novel high-speed low-power parallel prefix adder cell in 130-nm CMOS technology.Microelectronics J.2007381112001208
     [Google Scholar]
  35. RaniT.S. JainS.K. ChavanS.S. Design and analysis of low power approximate parallel prefix adder using hybrid logic styles.Microprocess. Microsyst.202179103476
     [Google Scholar]
  36. AgrawalA. KumarA. MukhopadhyayS. Design and analysis of energy-efficient approximate parallel prefix adders.Integration 20217993101
     [Google Scholar]
  37. WangX. XuZ. ZhangS. A low-power approximate parallel prefix adder using hybrid error compensation.IEEE Access20208219261219269
     [Google Scholar]
  38. SharmaS. SharmaA. A comprehensive review on low power adders design using approximate computing.5th International Conference on Computing, Communication and Security (ICCCS), Oct. 2020, pp. 1-7.
     [Google Scholar]
  39. RaniT.S. JainS.K. ChavanS.S. Design and performance analysis of low power approximate parallel prefix adder using hybrid logic styles.2020 4th International Conference on Electronics, Communication and Aerospace Technology (ICECA), June 2020 pp. 198-202.
     [Google Scholar]
  40. MittalR.K. JainS.K. NagariaR.K. Design of energy-efficient low power parallel prefix adder using approximate computing techniques.2nd International Conference on Advanced Computational and Communication Paradigms (ICACCP), Aug. 2020, pp. 1-5.
     [Google Scholar]
  41. GuptaS. RangaV. Design of a novel low power approximate parallel prefix adder using hybrid error correction. 202011th International Conference on Computing, Communication and Networking Technologies (ICCCNT), , July 2020 pp. 1-6.
     [Google Scholar]
  42. WangZ. YaoY. WangJ. Design and analysis of low-power approximate parallel prefix adders using hybrid approximate computing.International Conference on Computer, Information and Telecommunication Systems (CITS), July 2020 pp. 1-5.
     [Google Scholar]
  43. AlmansooriA.S. AljunidS.A. AljunidS.A. A review on approximate computing: Techniques, challenges, and applications.6th International Conference on Electrical and Electronic Engineering (ICEEE), Dec. 2019 pp. 1-6.
     [Google Scholar]
  44. AgrawalN. PalS.K. Low-power approximate parallel prefix adders with hybrid error correction.9th International Conference on Cloud Computing, Data Science & Engineering - Confluence, Jan. 2019, pp. 225-230.
     [Google Scholar]
  45. PalS. AgrawalN. PalS.K. A survey on low-power approximate parallel prefix adder designs.International Conference on Computational Intelligence and Knowledge Economy (ICCIKE), Dec. 2019, pp. 1-7.
     [Google Scholar]
  46. MittalS. PalS.K. A survey on low power approximate parallel prefix adder designs.8th International Conference on Cloud Computing, Data Science & Engineering - Confluence, Jan. 2018, pp. 130-135.
     [Google Scholar]
  47. JainS. RangaV. Approximate parallel prefix adders: A comprehensive review.International Conference on Intelligent Computing and Control Systems (ICICCS), June 2018, pp. 399-404.
     [Google Scholar]
  48. GargS. PalS.K. A survey on low-power approximate parallel prefix adder designs.2nd International Conference on Computing and Communications Technologies (ICCCT), , Feb. 2017, pp. 194-198.
     [Google Scholar]
  49. JainS. RangaV. A comprehensive review on low power approximate parallel prefix adders.International Conference on Computing, Communication, and Automation (ICCCA)2017, May 2017, pp. 207-212.
     [Google Scholar]
  50. NayakA. MahapatraA. MohantyS.K. Low power approximate parallel prefix adders: A review.2017 IEEE Uttar Pradesh Section International Conference on Electrical, Computer and Electronics Engineering (UPCON), Nov. 2017, pp. 178-182.
     [Google Scholar]
  51. MittalS. PalS.K. A survey on low power approximate parallel prefix adders.2016 6th International Conference - Cloud System and Big Data Engineering (Confluence), Jan. 2016 pp. 620-625.
     [Google Scholar]
/content/journals/raeeng/10.2174/0123520965311872240509092528
Loading
Performance Analysis of Approximate Parallel Prefix Adders Realized with Field-programmable Gate Array Technology
Recent Advances in Electrical & Electronic Engineering 18, 1072 (2025); https://doi.org/10.2174/0123520965311872240509092528
/content/journals/raeeng/10.2174/0123520965311872240509092528
/content/journals/raeeng/10.2174/0123520965311872240509092528
Loading

Data & Media loading...


  • Article Type:     Research Article
Keyword(s): approximate parallel prefix adders; arithmetic circuits; delay; FPGA; Kogge-Stone; ladner-fisher; power; Prefix adders

Most Cited Most Cited RSS feed

This is a required field
Please enter a valid email address
Approval was a Success
Invalid data
An Error Occurred
Approval was partially successful, following selected items could not be processed due to error
Please enter a valid_number test