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2000
Volume 18, Issue 7
  • ISSN: 2352-0965
  • E-ISSN: 2352-0973

Abstract

Background

Higher power consumption raises chip temperature because it draws more current from the power source, which directly affects how long the batteries survive in portable devices. High temperature affects the dependability and functionality of a circuit, requiring more complex packaging and cooling strategies. One of the most significant challenges in VLSI design is power consumption. The power consumption of the circuit rises with both transistor density and chip complexity. In addition, one of the essential building blocks of hardware in the majority of VLSI applications and digital signal processing systems is the multiplier.

Aims and Objective

This study aimed to design and compare array multiplier, Vedic multiplier, and Wallace tree multiplier using variable bit lengths.

Methodology

In this paper, authors designed array multiplier, Vedic multiplier, and Wallace tree multiplier using variable bit lengths. For comparison, the VIVADO tool was used to simulate and synthesize multiplier outputs.

Results

Wallace tree multipliers resulted in 31.153mW, 13.220mW, 4.099mW, and 0.988 mW of power dissipation for 16-bit, 8-bit, 4-bit, and 2-bit, respectively. The best multiplier was designed using different logic like AOI, OAI, NAND-NAND, and NOR-NOR and was compared based on power dissipation. It was observed that 2.256mW power dissipation was observed for NOR-NOR logic, which was minimal among other logics.

Conclusion

The 4-bit Wallace multiplier using NOR-NOR logic was used for FPGA implementation, which can be used in digital signal processing applications.

© 2025 Bentham Science Publishers
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2024-04-02
2025-08-18

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References

  1. VLSI Design CycleAvailable from: https://www.geeksforgeeks.org/vlsi-design-cycle/
  2. MarthaP. KajalN. KumariP. RahulR. An efficient way of implementing high speed 4-Bit advanced multipliers in FPGA.2018 2nd International Conference on Electronics, Materials Engineering & Nano-Technology,Kolkata, India, 04-05 May 2018, pp. 1-5 .10.1109/IEMENTECH.2018.8465375
     [Google Scholar]
  3. KumarU.A. ChatterjeeS.K. AhmedS.E. Low-power compressor-based approximate multipliers with error correcting module.IEEE Embed. Syst. Lett.2022142596210.1109/LES.2021.3113005
     [Google Scholar]
  4. HemamithraK.G. Lakshmi PriyaS. LakshmirajanK. MohanraiR. RameshS.R. FPGA implementation of power efficient approximate multipliers.3rd IEEE International Conference on Recent Trends in Electronics, Information & Communication Technology,Bangalore, India, 18-19 May 2018, pp. 1281-1285.10.1109/RTEICT42901.2018.9012325
     [Google Scholar]
  5. SabetzadehF. MoaiyeriM.H. AhmadinejadM. An Ultra-efficient approximate multiplier with error compensation for error-resilient applications.IEEE Trans. Circuits Syst. II Express Briefs202370277678010.1109/TCSII.2022.3215065
     [Google Scholar]
  6. StrolloA.G.M. NapoliE. De CaroD. PetraN. SaggeseG. Di MeoG. Approximate multipliers using static segmentation: Error analysis and improvements.IEEE Trans. Circuits Syst. I Regul. Pap.20226962449246210.1109/TCSI.2022.3152921
     [Google Scholar]
  7. SayahiI. MachhoutM. TourkiR. FPGA implementation of matrix-vector multiplication using Xilinx system generator.International Conference on Advanced Systems and Electric Technologies,Hammamet, Tunisia, 22-25 March 2018, pp. 290-295.10.1109/ASET.2018.8379873
     [Google Scholar]
  8. AhmadinejadM. MoaiyeriM. H. Energy and quality-efficient approximate multipliers for neural network and image processing applications.IEEE Trans. Emerg. Top. Comput.20221021105111610.1109/TETC.2021.3072666
     [Google Scholar]
  9. RamG.C. SubbaraoM.V. KumarD.G. TerlapuS.K. FPGA implementation of 16-Bit wallace multiplier using HCA.Advances in Micro-Electronics, Embedded Systems and IoT. Lecture Notes in Electrical Engineering. ChakravarthyV.V.S.S.S. Flores-FuentesW. BhatejaV. BiswalB. SingaporeSpringer202283810.1007/978‑981‑16‑8550‑7_40
     [Google Scholar]
  10. Van ToanN. LeeJ.G. FPGA-based multi-level approximate multipliers for high-performance error-resilient applications.IEEE Access20208254812549710.1109/ACCESS.2020.2970968
     [Google Scholar]
  11. VinodK. VishweshK.A. A novel approach to design complex multiplier using vedic sutras.International Conference on Circuits, Communication, Control and Computing,Bangalore, India, 21-22 Nov. 2014, pp. 398-403.
     [Google Scholar]
  12. BhandariJ.K. VermaY.K. SinghL. GuptaS.K. A novel design of high-performance hybrid multiplier.J. Circuits Syst. Comput.20223115225026810.1142/S0218126622502681
     [Google Scholar]
  13. ThakurG. SohalH. JainS. Power area optimized approximate multiplier design for image fusion.Circuits Syst. Signal Process.2023432288231910.1007/s00034‑023‑02559‑0
     [Google Scholar]
  14. KajalV.K.S. SharmaV.K. An efficient low power method for FinFET domino OR logic circuit.Microprocess. Microsyst.20229510471910.1016/j.micpro.2022.104719
     [Google Scholar]
  15. KoluK.P.A. KalyaniP. Vedic divider: A novel design for deconvolution algorithm based on vedic math.Fifth International Conference on Electrical, Computer and Communication Technologies (ICECCT),Erode, India, 22-24 Feb. 2023, pp. 1-8.
     [Google Scholar]
  16. JagadguruS.S. KalyaniP. Vedic Mathematics: Sixteen Simple Mathematical Formulae from the Vedas (PB)MLBD PublicationsNew Dehli20081367
     [Google Scholar]
  17. ThakurG. SohalH. JainS. A novel asic-based variable latency speculative parallel prefix adder for image processing application.Circuits Syst. Signal Process.202140115682570410.1007/s00034‑021‑01741‑6
     [Google Scholar]
  18. KoikeS. KaizuK. KishimotoT. High-speed signal transmission at the front of a bookshelf packaging system.IEEE Trans. Compon. Packaging Manuf. Technol. Part B197720435336010.1109/96.641503
     [Google Scholar]
  19. RavindranA. FPGA implementation of approximate multiplier with edge detection application.6th International conference on Intelligent Computing and Control Systems,Madurai, India, 25-27 May 2022, pp. 287-291.2022
     [Google Scholar]
  20. ThakurG. SohalH. JainS. A novel parallel prefix adder for optimized Radix-2 FFT processor.Multidimens. Syst. Signal Process.20213231041106310.1007/s11045‑021‑00772‑1
     [Google Scholar]
  21. ShrivastavaS. KaurA. Implementation and analysis on 4x4 multiplier using genesys fpga board.2023 International Conference on Sustainable Computing and Smart Systems (ICSCSS),Coimbatore, India, 14-16 June 2023, pp. 1174-1178.10.1109/ICSCSS57650.2023.10169387
     [Google Scholar]
  22. RozaD. A review in advanced digital signal processing systems.Intern. J. Elec. Comput. Eng.2021153122127
     [Google Scholar]
  23. KaustubhM. Vedic mathematics for digital signal processing operations: A review.Intern. J. Comput. Appl.20151131014
     [Google Scholar]
  24. BurenevaO. MironovS. Fast FPGA-based multipliers by constant for digital signal processing systems.Electronics202312360510.3390/electronics12030605
     [Google Scholar]
  25. ThakurG. SohalH. JainS. Implementation of a robust framework for low power approximate multiplier using novel 3:2 and 4:2 compressor for image processing applications.Micro Nanosyst.202315322323910.2174/0118764029270767231025052434
     [Google Scholar]
  26. GarimaT. ShrutiJ. HarshS. Current issues and emerging techniques for VLSI testing: A review, measurement.Sensors202224100497
     [Google Scholar]
  27. PradeepK.K. GajendraS. Design and comparison of 8x8 wallace tree multiplier using CMOS and GDI technology.IOSR2017745762
     [Google Scholar]
  28. Vaibhavi SolankiA.D. Design of low-power wallace tree multiplier architecture using modular approach.Circuits, Systems, and Signal Processing202140944074427
     [Google Scholar]
  29. Jagadeeswara RaoE. SamundiswaryP. Efficient design of modified wallace tree approximate multipliers based on imprecise compressors for error-tolerance application.Arabian J. Sci. Eng.20234942534270
     [Google Scholar]
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FPGA Implementation of Power-efficient Multipliers for Digital Signal Processing Applications
Recent Advances in Electrical & Electronic Engineering 18, 1036 (2025); https://doi.org/10.2174/0123520965220371240315054004
/content/journals/raeeng/10.2174/0123520965220371240315054004
/content/journals/raeeng/10.2174/0123520965220371240315054004
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  • Article Type:     Research Article
Keyword(s): bit stream; fast speed; FPGA; logics; Multipliers; power efficient

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