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2000
Volume 18, Issue 7
  • ISSN: 2352-0965
  • E-ISSN: 2352-0973

Abstract

Background

With the advancement in technology nodes and scaling trends, the majority of the device performance depends upon the interconnections made between two or more devices. With these scaling trends, frequency plays a vital role. As the technology decreases, frequency tends to rise to giga-hertz. This increase in frequency gives rise to inductance parameters in the interconnect circuits. For long wires, the inductive impedance can become comparable to the resistive component due to which performance degradation can be observed along with overshoot and crosstalk issues that can no longer be ignored.

Methods

This article aims to examine the delay model and reconstruct an interconnect circuit that serves as a transmission line, ranging in length from 1 mm to 10 mm.

Results

By keeping the frequency high, low voltage and rise/ fall time, performance parameters such as delay, power consumption, and overshoot are observed.

Conclusion

The interconnect structure is compared with another state-of-the-art technique.

© 2025 Bentham Science Publishers
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2025-10-03

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Design of Global RLC Interconnect Circuit with Analytical Delay Model
Recent Advances in Electrical & Electronic Engineering 18, 1053 (2025); https://doi.org/10.2174/0123520965298473240314065311
/content/journals/raeeng/10.2174/0123520965298473240314065311
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  • Article Type:     Research Article
Keyword(s): CMOS; delay; Interconnect; power consumption; transmission lines; VLSI

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