Parallel Full Search Algorithm for Motion Estimation on Graphic Processing Unit

Background: Advances in video compression technology have been driven by everincreasing processing power available in software and hardware. Methods: The emerging High-Efficiency Video Coding (HEVC) standard aims to provide a doubling in coding efficiency with respect to the H.264/AVC high profile, delivering the same video quality at half the bit rate. Results: Thus, the results show high computational complexity. In both standards, the motion estimation block presents a significant challenge in clock latency since it consumes more than 40% of the total encoding time. For these reasons, we proposed an optimized implementation of this algorithm on a low-cost NVIDIA GPU developed with CUDA language. Conclusion: This optimized implementation can provide high-performance video encoder where the speed reaches about 85.