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2000
Volume 19, Issue 2
  • ISSN: 1872-2105
  • E-ISSN: 2212-4020

Abstract

Introduction

This work proposes a Double-Gate (DG) MOSFET with a Single Material made of Silicon On-Insulator (SOI). The Lanthanum Oxide material with a high k-dielectric constant has been used as an interface between two gates and the channel. The Monte Carlo analysis has been used to determine the Conduction Band Energy (Ec) profiles and electron sheet carrier densities (n) for a Silicon channel thickness (t) of 10 nm at 0.5 V gate drain-source voltages. The transverse electric fields are weak at the midchannel of DG SOI MOSFETs, where quantum effects are encountered. The Monte Carlo simulation has been confirmed to be effective for high-energy transport. A particle description reproduces the granularity property of the transport for nanoscale modeling.

Methods

This work utilizes a Monte Carlo (MC) Simulation for the proposed Double Gate Single Material Silicon On Insulator MOSFET with (LaO=2 nm) as dielectric oxide on upper and lower gate material. The electrical properties of the DG SOI MOSFETs with Lanthanum Oxide were analyzed using Monte Carlo simulation, including the conduction band energy, electric field, potential distribution, particle movement, and average velocity.

Results

The peak electric field (E) simulation results and an average drift velocity (υ) of 6x105 V/cm and 1.6x107 cm/s were obtained, respectively. The conduction band energy for the operating region of the source has been observed to be 4% to the drain side, which obtained a value of -0.04 eV at the terminal end.

Conclusion

This proposed patent design, such as double-gate SOI-based devices, is the best suggestion for significant scalability challenges. Emerging technologies reach the typical DG SOI MOSFET's threshold performance when their geometrical dimensions are in the nanometer region. This device based on nanomaterial compounds has been more submissive than conventional devices. The nanomaterials usage in the design is more suitable for downscaling and reducing packaging density.

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References

  1. ReddyG.V. KumarM.J. Investigation of the novel attributes of a single-halo double gate SOI MOSFET: 2D simulation study.Microelectronics200435976176510.1016/j.mejo.2004.06.003
    [Google Scholar]
  2. KhakifiroozA. ChengK. JagannathanB. KulkarniP. SleightJ. ShahrjerdiD. ChangJ. LeeS. LiJ. BuH. GauthierR. DorisB. ShahidiG. Fully depleted extremely thin SOI for mainstream 20 nm low-power technology and beyond.IEEE International Solid-State Circuits Conference - (ISSCC).San Francisco, CA, USA. 2010; pp. 152-153.10.1109/ISSCC.2010.5434014
    [Google Scholar]
  3. VeeraraghavanS. FossumJ.G. Short-channel effects in SOI MOSFETs.IEEE Trans. Electron Dev.198936352252810.1109/16.19963
    [Google Scholar]
  4. SrivastavaVM. YadavKS SinghG. Double-pole four-throw RF CMOS switch design with double-gate transistors2010 Annual IEEE India Council Int. Conference (INDICON)India20101410.1109/INDCON.2010.5712754
    [Google Scholar]
  5. SrivastavaV.M. Scaling effect of CSDG MOSFET: A device beyond 22 nm technology4th Int. Conf. on Advanced Computing and Communication Systems (ICACCS)India20171510.1109/ICACCS.2017.8014562
    [Google Scholar]
  6. VeeraraghavanS. FossumJ.G. A physical short-channel model for the thin-film SOI MOSFET applicable to device and circuit CAD.IEEE Trans. Electron Dev.198835111866187510.1109/16.7399
    [Google Scholar]
  7. SrivastavaV.M. Relevance of VEE programming for measurement of MOS device parametersIEEE International Advance Computing Conference (IACC)Patiala, India2009205209978-981-08-2465-5
    [Google Scholar]
  8. KumarM.J. ChaudhryA. Two-dimensional analytical modeling of fully depleted DMG SOI MOSFET and evidence for diminished SCEs.IEEE Trans. Electron Dev.200451456957410.1109/TED.2004.823803
    [Google Scholar]
  9. ChaudhryA. KumarM.J. Investigation of the novel attributes of a fully depleted dual-material gate SOI MOSFET.IEEE Trans. Electron Dev.20045191463146710.1109/TED.2004.833961
    [Google Scholar]
  10. JoachimH.O. YamaguchiY. IshikawaK. InoueY. NishimuraT. Simulation and two-dimensional analytical modeling of subthreshold slope in ultrathin-film SOI MOSFETs down to 0.1 mu m gate length.IEEE Trans. Electron Dev.199340101812181710.1109/16.277338
    [Google Scholar]
  11. GámizF. SampedroC. DonettiL. GodoyA. Monte-carlo simulation of ultra-thin film silicon-on-insulator MOSFETS.Frontiers in Electronics201413210.1142/9789814583190_0001
    [Google Scholar]
  12. WinsteadB. RavaioliU. Simulation of Schottky barrier MOSFETs with a coupled quantum injection/Monte Carlo technique.IEEE Trans. Electron Dev.20004761241124610.1109/16.842968
    [Google Scholar]
  13. DasS.K. NandaU. BiswalS.M. PandeyC.K. GiriL.I. Performance analysis of gate-stack dual-material DG MOSFET using work-function modulation technique for lower technology nodes.Silicon2021142965297310.1007/s12633‑021‑01095‑3
    [Google Scholar]
  14. VimalaP. BalamuruganN.B. Quantum mechanical compact modeling of symmetric double-gate MOSFETs using variational approach.J. Semicond.201233303400110.1088/1674‑4926/33/3/034001
    [Google Scholar]
  15. TaurY. NingT.H. Fundamentals of modern VLSI devices.Cambridge, UKUniversity Press Cambridge1998
    [Google Scholar]
  16. Lopez-VillanuevaJ.A. Cartujo-CassinelloP. GamizF. BanqueriJ. PalmaA.J. Effects of the inversion-layer centroid on the performance of double-gate MOSFETs.IEEE Trans. Electron Dev.200047114114610.1109/16.817579
    [Google Scholar]
  17. FrankLaux Monte Carlo simulation of a 30 nm dual-gate MOSFET: How short can Si go?International Technical Digest on Electron Devices meeting.San Francisco, CA, USA. 1992; pp. 553-55610.1109/IEDM.1992.307422
    [Google Scholar]
  18. KathawalaG.A. WinsteadB. RavaioliU. Monte Carlo simulations of double-gate MOSFETs.IEEE Trans. Electron Dev.200350122467247310.1109/TED.2003.819699
    [Google Scholar]
  19. MadadiD. OroujiA.A. Investigation of short channel effects in SOI MOSFET with 20 nm channel length by a β-Ga2O3 layer.ECS J. Solid-State Sci. Technol.202094045002
    [Google Scholar]
  20. KhakifiroozA. ChengK. KulkarniP. CaiJ. PonothS. KussJ. ShahidiG. Challenges and opportunities of extremely thin SOI (ETSOI) CMOS technology for future low power and general-purpose system-on-chip applications.Proceedings of 2010 International Symposium on VLSI Technology, System and Application.Hsinchu, Taiwan. 2010; pp.26-28.10.1109/VTSA.2010.5488928
    [Google Scholar]
  21. RavishankarR. KathawalaG. RavaioliU. HasanS. LundstromM. Comparison of monte carlo and NEGF simulations of double gate MOSFETs.J. Comput. Electron.200541-2394310.1007/s10825‑005‑7104‑y
    [Google Scholar]
  22. MaduagwuU.A. SrivastavaV.M. Sensitivity of lightly and heavily dopped cylindrical surrounding double-gate (CSDG) MOSFET to process variation.IEEE Access2021914254114255010.1109/ACCESS.2021.3121315
    [Google Scholar]
  23. MaduagwuU.A. SrivastavaV.M. Assessment of quantum scaling length model for cylindrical surrounding double-gate (CSDG) MOSFET.Micro Nanosyst.202113446747210.2174/1876402913666210222141301
    [Google Scholar]
  24. Sampedro-MatarinC. GamizF. GodoyA. RuizF.J.G. The multivalley effective conduction band-edge method for monte carlo simulation of nanoscale structures.IEEE Trans. Electron Dev.200653112703271010.1109/TED.2006.882782
    [Google Scholar]
  25. GamizF. FischettiM.V. Monte Carlo simulation of double-gate silicon-on-insulator inversion layers: The role of volume inversion.J. Appl. Phys.200189105478548710.1063/1.1358321
    [Google Scholar]
  26. FischettiM.V. LauxS.E. Monte Carlo study of electron transport in silicon inversion layers.Phys. Rev. B Condens. Matter19934842244227410.1103/PhysRevB.48.224410008617
    [Google Scholar]
  27. Saint-MartinJ. BournelA. Aubry-FortunaV. MonsefF. ChassatC. DollfusP. Monte Carlo simulation of double gate MOSFET including multi sub-band description.J. Comput. Electron.20065443944210.1007/s10825‑006‑0043‑4
    [Google Scholar]
  28. GámizF. RoldánJ.B. GodoyA. CarcellerJ.E. CartujoP. Double gate silicon on insulator transistors. A Monte Carlo study.Solid-State Electron.200448693794510.1016/j.sse.2003.12.017
    [Google Scholar]
  29. IwataH. MatsudaT. OhzoneT. An accurate and computationally efficient method for device simulation with scattering in nanoscale double-gate metal–oxide-semiconductor transistors.Jpn. J. Appl. Phys.2006455A4009401110.1143/JJAP.45.4009
    [Google Scholar]
  30. SangiorgiE. PalestriP. EsseniD. FiegnaC. SelmiL. The Monte Carlo approach to transport modeling in deca-nanometer MOSFETs.Solid-State Electron.20085291414142310.1016/j.sse.2008.04.007
    [Google Scholar]
  31. SrivastavaV. Signal processing for wireless communication MIMO system with nano-scaled CSDG MOSFET based DP4T RF Switch.Recent Pat. Nanotechnol.201591263210.2174/18722105090115031110095425986227
    [Google Scholar]
  32. ColingeJ.P. Multi-gate SOI MOSFETs.Microelectron. Eng.2007849-102071207610.1016/j.mee.2007.04.038
    [Google Scholar]
  33. ErnstT. CristoloveanuS. GhibaudoG. OuisseT. HoriguchiS. OnoY. TakahashiY. MuraseK. Ultimately thin double-gate SOI MOSFETs.IEEE Trans. Electron Dev.200350383083810.1109/TED.2003.811371
    [Google Scholar]
  34. ReddyG.V. KumarM.J. A New Dual-Material Double-Gate (DMDG) nanoscale soi mosfet—two-dimensional analytical modeling and simulation.IEEE Trans. Nanotechnol.20054226026810.1109/TNANO.2004.837845
    [Google Scholar]
  35. ParamasivamP. GowthamanN. SrivastavaV.M. Design and analysis of InP/InAs/AlGaAs based Cylindrical Surrounding Double-Gate (CSDG) MOSFETs with La2O3 for 5-nm technology.IEEE Access2021915956676
    [Google Scholar]
  36. OroujiA.A. RahimianM. Leakage current reduction in nanoscale fully-depleted SOI MOSFETs with modified current mechanism.Curr. Appl. Phys.20121251366137110.1016/j.cap.2012.03.029
    [Google Scholar]
  37. WangQ. ChengX. ZhengL. YeP. LiM. ShenL. LiJ. ZhangD. GuZ. YuY. Enhanced interfacial and electrical characteristics of 4H-SiC MOS capacitor with lanthanum silicate passivation interlayer.Appl. Surf. Sci.201741032633110.1016/j.apsusc.2017.03.114
    [Google Scholar]
  38. WangQ. ChengX. ZhengL. ShenL. ZhangD. GuZ. QianR. CaoD. YuY. Influence of LaSiOx passivation interlayer on band alignment between PEALD-Al2O3 and 4H-SiC determined by X-ray photoelectron spectroscopy.Appl. Surf. Sci.20184281610.1016/j.apsusc.2017.09.099
    [Google Scholar]
  39. HamidF.A. AliasN.E. JohariZ. HamzahA. TanM.L.P. IsmailR. Effect of low-k oxide thickness variation on gate-all-around floating gate with optimized SiO 2 /La 2 O 3 tunnel barrier.Mater. Res. Express20196111150c610.1088/2053‑1591/ab2869
    [Google Scholar]
  40. NichauA. OzbenE. D. SchneeM. LopesJ. M. J. BesmehnA. LuysbergM. MantlS. Lanthanum Lutetium oxide integration in a gate-first process on SOI MOSFETs.Ulis 2011 Ultimate Integration on Silicon.Cork, Ireland14-16 Mar201110.1109/ULIS.2011.5757952
    [Google Scholar]
  41. GowthamanN. SrivastavaV.M Parametric analysis of CSDG MOSFET with La2O3 gate oxide: Based on electrical field estimation.IEEE Access202191594213110.1109/ACCESS.2021.3131980
    [Google Scholar]
  42. LiuL. TangW. LaiP. Advances in la-based high-k dielectrics for MOS applications.Coatings20199421710.3390/coatings9040217
    [Google Scholar]
  43. Ortiz-CondeA. García SánchezF.J. MuciJ. Rigorous analytic solution for the drain current of undoped symmetric dual-gate MOSFETs.Solid-State Electron.200549464064710.1016/j.sse.2005.01.017
    [Google Scholar]
  44. GowthamanN. SrivastavaVM. Investigations on Cylindrical Surrounding Double-Gate (CSDG) MOSFET using AlxGa1-xAs/InP: Pt with La2O3 oxide layer for fabrication.Recent Pat. Nanotechnol.20241833748510.2174/187221051766623042716344737132315
    [Google Scholar]
  45. ParamasivamP. GowthamanN. SrivastavaV.M. Design and analysis of gallium arsenide-based nanowire using coupled non-equilibrium green function for rf hybrid applications.Nanomaterials202313695910.3390/nano1306095936985854
    [Google Scholar]
  46. CobianuO. SoffkeO. GlesnerM. A Verilog-A model of an undoped symmetric dual-gate MOSFET.Adv. Radio Sci.2006430330610.5194/ars‑4‑303‑2006
    [Google Scholar]
  47. ArefiniaZ. Nonequilibrium Green’s function treatment of a new nanoscale dual-material double-gate MOSFET.Physica E20114351105111010.1016/j.physe.2011.01.010
    [Google Scholar]
  48. WinsteadB. RavaioliU. A quantum correction based on schrodinger equation applied to Monte Carlo device simulation.IEEE Trans. Electron Dev.200350244044610.1109/TED.2003.809431
    [Google Scholar]
  49. VenugopalR. PaulssonM. GoasguenS. DattaS. LundstromM.S. A simple quantum mechanical treatment of scattering in nanoscale transistors.J. Appl. Phys.20039395613562510.1063/1.1563298
    [Google Scholar]
  50. ManglaA. SalleseJ.M. SampedroC. GamizF. EnzC. Role of the gate in ballistic nanowire SOI MOSFETs.Solid-State Electron.2015112242810.1016/j.sse.2015.02.010
    [Google Scholar]
  51. (a) OroujiA.A. RahimifarA. JoziM. A novel double-gate SOI MOSFET to improve the floating body effect by dual SiGe trench.J. Comput. Electron.201615253754410.1007/s10825‑016‑0801‑x
    [Google Scholar]
  52. (b) SukSD SadanaD ChenT-C. Single process double gate and variable threshold voltage MOSFET.WO Patent 202307903A12023
    [Google Scholar]
  53. ChowdhuryD. DeB.P. AppasaniB. SinghN.K. KarR. MandalD. BizonN. ThounthongP. A novel dielectric modulated gate-stack double-gate metal-oxide-semiconductor field-effect transistor-based sensor for detecting biomolecules.Sensors2023236295310.3390/s2306295336991665
    [Google Scholar]
  54. MohapatraS.K. PradhanK.P. ArtolaL. SahuP.K. Estimation of analog/RF figures-of-merit using device design engineering in gate stack double gate MOSFET.Mater. Sci. Semicond. Process.20153145546210.1016/j.mssp.2014.12.026
    [Google Scholar]
  55. LiZ. JiangY. ZhangL. A Single-Halo Dual-Material Gate SOI MOSFET.2007 International Workshop on Electron Devices and Semiconductor Technology (EDST).Tsinghua University. 2007; pp. 66-69.10.1109/EDST.2007.4289779
    [Google Scholar]
  56. GowthamanN. ParamasivamP. SrivastavaV.M. Parametric analysis of indium gallium arsenide wafer-based thin body (5 nm) double-gate MOSFETs for hybrid RF applications.Recent Pat. Nanotechnol.20241833354910.2174/187221051766623060209534737723950
    [Google Scholar]
  57. SunY. XiaoningW. JiaQ. YangJ. Preparation of modified rare earth lanthanum oxide/polypropylene nonwoven fabric by melt-blown method.J. Phy.: Conf. Series202221941610.1088/1742‑6596/2194/1/012046
    [Google Scholar]
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