FPGA Implementation of Vedic Squarer for Communication Systems

Background: The squarer or squaring circuit is extensively used in communication systems as a mathematical function with applications of frequency doublers, Finite Impulse Response (FIR) filters, peak amplitude detectors, digital processors and analog multipliers, etc. and especially for square law detection circuits. Objectives: Vedic multipliers are popular mainly for their simplicity in the literature of digital multipliers. Methods: Recently, proposed 2-bit square calculator or self-multiplier already gained the attraction of the researchers. Results & Conclusion: In this paper, two bits squarer or self-multiplier or square calculator has been successfully coded using VHDL, verified in Xilinx tool and finally implemented in popular FPGA Spartan kit.