Recent Advances in Electrical & Electronic Engineering - Volume 11, Issue 2, 2018
Volume 11, Issue 2, 2018
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An Optimal Design of Super-Directive Dipole Linear Antenna Array Using Gravitational Search Algorithm and Large Perfect Reflecting Surface
More LessAuthors: Saumendra K. Mohanty and Biswa Binayak MangarajBackground: This article presents a 12-element Dipole Linear Array Antenna (DLAA) optimization using Gravitational Search Algorithm (GSA) to find optimal design parameters such as lengths corresponding to each dipole and spacing corresponding to separation between two neighbor dipoles. Methods: GSA optimizes the design parameters to offer the desired performance parameters such as high Directivity (DR), high Front to Back Ratio (FBR), high Front-to-Maximum-Side-Lobe-Level (FSL), and low Half-Power-Beam-Width (HBW) using a simple weighted sum type multi-objective function. Results: After optimization, the performance parameter DR is improved further by placing a large perfect reflecting surface (PRS) close to one side that is perpendicular to the axis of the array to achieve a Super-Directive DLAA (SDLAA). Conclusion: While analysing the DLAA, mutual coupling is taken into account for numerical analysis using Method of Moment (MoM).
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High CMRR Wide Bandwidth Instrumentation Amplifier Based on VDBA
More LessAuthors: Priyanka Gupta, Neeta Pandey and Rajeshwari PandeyBackground: In this paper, a novel instrumentation amplifier (IA) based on voltage differencing buffered amplifier (VDBA) is presented. The proposed IA consists of a single VDBA and a resistor and offers high common-mode rejection ratio (CMRR). The effects of non-idealities of the VDBA are analyzed and the corresponding mathematical formulation is derived. Methods: Theoretical analysis of the proposed circuit is verified through SPICE simulation using 180nm technology process parameters. Both frequency and transient responses are shown. Output and input noise densities are formulated for the proposed circuit and verified through the simulation results. Results: A CMRR magnitude of 198 dB with 3dB bandwidth of 2.81MHz is obtained for the proposed configuration. Conclusion: To investigate the effect of mismatches on the CMRR performance of the proposed circuit, Monte Carlo statistical analysis is also performed.
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