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2000
Volume 17, Issue 3
  • ISSN: 1876-4029
  • E-ISSN: 1876-4037

Abstract

Background

Emerging technologies aim to enhance processor speed, reduce chip sizes, and minimize power consumption in various electronic devices, including Smartphone’s.

Aim

The demand for improved battery life and low power consumption is indeed a significant challenge in the industry. Carbon nanotube field-effect transistors (CNTFETs) are one of the potential solutions being explored to address these challenges. The implementation of a full adder using CNTFETs can potentially leverage the benefits of these nanoscale devices. This paper introduces a novel approach to designing a 1-bit full adder cell with a focus on low voltage and low power requirements.

Methods

The proposed design combines pass transistor and transmission gate logic in a hybrid multiplexer-based configuration. The proposed full adder circuit utilizes a total of 14 transistors, resulting in a compact and efficient design.

Results

For +0.9 V supply voltage at 32-nm CNTFET technology, the power consumption is 0.0537 μW was found to be extremely low with lower propagation delay 8.7543 Ps and power-delay product (PDP) of 0.4701 aJ by the deliberate use of CMOS inverter and strong transmission gates. The performance analysis of different existing 1-bit full adder designs was compared concerning the newly proposed design in terms of power, delay, and power-delay product (PDP).

Conclusion

The implementation of an N-bit ripple carry adder utilizing the proposed full adder is finally presented. The results obtained from this analysis provide valuable insights into the power efficiency, speed, and overall performance of the proposed design. The performance of the proposed 1-bit full adder circuit was examined with 32-nm CNTFET technology at +0.9 V single-ended supply voltage using the Mentor Graphics Schematic Design Composer CAD tool.

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2025-09-01
2025-09-26

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Efficient Low Voltage Low Power 1-Bit Full Adder Design with Hybrid Multiplexer Approach Using 32-nm CNTFET Technology
Micro and Nanosystems 17, 232 (2025); https://doi.org/10.2174/0118764029346874250225232323
/content/journals/mns/10.2174/0118764029346874250225232323
/content/journals/mns/10.2174/0118764029346874250225232323
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  • Article Type:     Research Article
Keyword(s): CNTFET technology; digital integrated circuits; Full adders; hybrid logic; performance analysis; ripple carry adder

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