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image of TAARBM: A Truncated Adaptive Approximate Radix-8 Booth Multiplier for Image Processing Applications

Abstract

Introduction

Approximate computing is one of the techniques used to balance trade-offs between power, speed, and area in a resource-limited environment. Mainly, a large amount of power consumption and significant delay are caused by the arithmetic operations, in which the multiplication process generates more power consumption and high latency. In order to save energy and increase speed, an approximate multiplier is a good candidate for use in error-resilient applications like signal and image processing. This study proposes a truncated adaptive approximate radix-8 Booth multiplier (TAARBM). It aims to apply partial product truncation to construct an approximation multiplier design for error-tolerant applications, such as image processing.

Methods

The truncation strategy is adopted to minimize the partial product array (PPA) of the radix-8 Booth multiplier, as an additional PPA creates complexity in the operations. Moreover, the Booth encoder in the radix-8 Booth multiplier is enhanced with an Approximate Booth Encoder (ABE), which replaces adders with simple shift-logic operations to speed up the operation. The path Selectable and Reconfigurable Hybrid Adder (pSRHA) is introduced in the TAARBM architecture to minimize the delay. The design is coded in Verilog-HDL, simulated on the Xilinx Vivado simulator, and implemented on an FPGA board.

Results

The simulation results demonstrate that the proposed 16-bit TAARBM consumes 4.110 power and 1.805 ns delay. The proposed design accomplishes error metrics of 402.96 MED, 0.00975 MRED, 1300 AED, and 0.0120 ARE.

Discussion

The simulation results show the proposed design's high-speed operation. Moreover, the proposed approximate multiplier is designed with a low error rate, as shown by performing different error metrics like MED, MRED, AED, and ARE. In addition, the FIR filter is designed with the proposed TAARBM to perform the image denoising process on five benchmark images. For this application, the image quality measures, such as PSNR and SSIM, are calculated, which are higher for the proposed design.

Conclusion

The comparison of the obtained results with existing references proves the present validity of the current work. Various error metrics and synthesis results validate the effectiveness of the proposed approximate multiplier. Moreover, the proposed multiplier is used in an image processing application for the denoising process.

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2025-08-22
2026-02-27

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TAARBM: A Truncated Adaptive Approximate Radix-8 Booth Multiplier for Image Processing Applications
Bentham Science Publishers ; https://doi.org/10.2174/0118764029361847250810175040
/content/journals/mns/10.2174/0118764029361847250810175040
/content/journals/mns/10.2174/0118764029361847250810175040
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  • Article Type:     Research Article
Keywords: booth multiplier ; partial product ; digital arithmetic ; approximate multiplier ; filtering ; image processing ; hardware ; Approximate computing

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