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- ISSN: 1573-4137
- E-ISSN: 1875-6786
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A Model to Improve Analysis of CNTFET Logic Gates in Verilog-A-Part I: Static Analysis
- Source: Current Nanoscience, Volume 11, Issue 4, Aug 2015, p. 515 - 526
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- 01 Aug 2015
Abstract
In this paper we have implemented a simple DC model for CNTFETs already proposed by us in order to carry out static analysis of basic digital circuits, with a significant improvement compared to Wong model. In particular we have obtained a lighter ensuring compile and shorter execution time, without losing in accuracy.
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