Circuit Level Issues of Interconnect Pipelining in Nanoscale Integrated Circuits

With continuous scaling of semiconductor technologies, integrated circuit (IC) design enters into interconnectcentric nanometer regime, and aggressive optimization through repeater insertion, wire sizing and improved metallization are no longer adequate to resolve the discrepancy between device and wire delays. In this situation unconventional methodologies like insertion of sequential elements in interconnects lines - a concept that has become known as interconnect pipelining - are required to find acceptable solution beyond traditional buffer-insertion based interconnect systems. This paper provides a survey of the issues and challenges in realizing interconnect pipelining technique. A set of analytical models is developed to illustrate the impacts of clock skew and jitter on the minimum number, position and the feasible region of inserted flip-flops for interconnect pipelining. Based on that, a detailed analysis for the dependency of power consumption and bit-error-rate (BER) on the number of flip-flops inserted and repeater size is performed. For the best tradeoff between the wire delay, BER and power consumption, a methodology is developed to optimize the repeater size and the number of flip-flops inserted which maximize a user-specified figure of merit.