High-Performance Mixed Signal VLSI Design For Multimode Demodulator
- Authors: R. Kabilan1, J. Zahariya Gabrie2, Ravi R.3, M. Philip Austin4
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View Affiliations Hide Affiliations1 Department of ECE, Francis Xavier Engineering College, Affiliated with Anna University, 103/G2, Bypass Road, Vannarpettai, Tirunelveli, Tamil Nadu 627003, India 2 Department of Electronics and Communication Engineering, Francis Xavier Engineering College, Tirunelveli, India 3 Department of Electronics and Communication Engineering, Francis Xavier Engineering College, Tirunelveli, India 4 Department of ECE, Francis Xavier Engineering College, Affiliated with Anna University, 103/G2, Bypass Road, Vannarpettai, Tirunelveli, Tamil Nadu 627003, India
- Source: Intelligent Technologies for Research and Engineering , pp 150-167
- Publication Date: July 2024
- Language: English
High-Performance Mixed Signal VLSI Design For Multimode Demodulator, Page 1 of 1
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A mixed signal quadrature demodulator was suggested in this study. In 90 nm CMOS technology, to get the desired frequency range, a quadrature VCO is employed. The fast speed is achieved with a three-bit ADC. Unused ADC construction components have been removed to conserve energy and space. Outputs obtained are used to meet the power needed in the mixed signal demodulator designed for multigigabit applications. QVCO, baseband AGC, frequency synthesizers, and IQ mixers, are all part of the demodulator. This displays the highest level of integration while using the least amount of electricity. To sample the symbols at optimal SNR, the baseband modem included a mixed signal timing recovery loop based on the Gardner timing error detector.
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