Compact Modeling for NBTI and CHC Effects
- Authors: Wenping Wang1, Vijay Reddy2, Srikanth Krishnan3, Yu Cao4
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View Affiliations Hide Affiliations1 Department of Electrical Engineering, Arizona State University, Tempe, AZ 85287, USA 2 External Development and Manufacturing, Texas Instruments, PO Box 650311, MS 3740, Dallas TX 75243, USA 3 External Development and Manufacturing, Texas Instruments, PO Box 650311, MS 3740, Dallas TX 75243, USA 4 Department of Electrical Engineering, Arizona State University, Tempe, AZ 85287, USA
- Source: Recent Topics on Modeling of Semiconductor Processes, Devices, and Circuits , pp 40-60
- Publication Date: September 2011
- Language: English
Compact Modeling for NBTI and CHC Effects, Page 1 of 1
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Negative Bias Temperature Instability (NBTI) and Channel Hot Carrier (CHC), which is also called Hot Carrier Injection (HCI), are the leading reliability concerns for nanoscale transistors. The de facto modeling method to analyze CHC is based on substrate current (Isub), which becomes increasingly problematic with technology scaling as various leakage components dominate Isub. In this work, we present a unified approach that directly predicts the change of key transistor parameters under various process and design conditions, for both NBTI and CHC effects. Using the general reaction-diffusion model and the concept of surface potential, the proposed method continuously captures the performance degradation across subthreshold and strong inversion regions. Models are comprehensively verified with an industrial 65nm technology. By benchmarking the prediction of circuit performance degradation with measured ring oscillator data and simulations of an amplifier, we demonstrate that the proposed method predicts the degradation very well. For 65nm technology, NBTI is the dominant reliability concern and the impact of CHC on circuit performance is relatively small.
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